1. Field of the Invention
The present invention relates to a divider, and particularly, relates to a subtraction-shift-type divider and a microcomputer including such divider
2. Description of the Related Art
A principle of subtraction shift-type-division which performs a subtraction between a dividend or partial remainder by RSD representation and a divisor by twos complement representation is shown in pages 748 to 756 of the IEEE, Journal of Solid-State Circuit, Vol. 25, No. 3 (June, 1990).
Though various propositions are made as a divider and a processor conforming to the division principle shown in this journal, typical ones are Japanese Patent Application Laid-Open No. 63-49836 (1988), Japanese Patent Application Laid-Open No. 3-102519 (1991) and Japanese Patent Application Laid-Open No. 2-112023 (1990)
A number by RSD (Redundant Signed Digit) representation is a numerical representation which represents the number of each digit, by {-1, 0, 1}, and is expressed as Y in the following expression. ##EQU1##
While, a number by twos complement representation is expressed as Z in the following expression. ##EQU2##
The above,mentioned number Y by RSD representation and the number Z by twos complement representation are added as shown in a schematic diagram of FIG. 1, and their sum S is obtained as a number by RSD representation shown in the following expression. ##EQU3##
In FIG. 1, symbols of large .largecircle. respectively designate full adders, arid symbols of small .largecircle. respectively designate inverted inputs to or inverted outputs from the full adders.
FIG. 2(a) is a schematic diagram showing inputs and outputs to and from the full adder shown in FIG. 1, and
FIG. 2(b) is a truth table therebetween.
While, the number Y by RSD representation and the number Z by twos complement representation are subtracted as shown in a schematic diagram of FIG. 3, and their difference D is obtained is the number by RSD representation shown in the following expression. ##EQU4##
In FIG. 3, in the same way as FIG. 1, the symbols of large C) respectively designate the full adders and the symbols of small .largecircle. respectively designate the inverted inputs to or the inverted outputs from the full adders
Truth tables of the full adders shown in FIG. 3 are similar to that shown in FIG. 2(b).
Such addition and subtraction of the number Y by RSD representation and the number Z by twos complement representation can be performed rapidly because of free from carry propagations.
In a subtraction-shift-type divider, a quotient digit q.sub.j is selected to satisfy the following expressions (1) and (2) with respect to the partial remainder (dividend) R.sub.j and the divisor D. EQU R.sub.j+1 =2.multidot.(R.sub.j -q.sub.j .multidot.D) (1) EQU -2.multidot..vertline.D.vertline.&lt;R.sub.j+1 &lt;2.multidot..vertline.D.vertline. (2)
A selective process of the quotient digit q.sub.j satisfying the expressions (1) and (2) is not one and only but somewhat optional. For example, in a restoring division, with respect to the positive partial remainder (dividend) R.sub.j and divisor D, the quotient q.sub.j is EQU q.sub.j .epsilon.{0, 1}, and
in an unrestoring division, EQU q.sub.j .epsilon.{-1, 1}
It is also possible to have EQU q.sub.j .epsilon.{-1, 0, 1},
and these are used in the principle of division in the aforementioned journal.
Now, in the principle of division in the aforementioned journal, the quotient digit q.sub.j is decided according to a table as shown in FIG. 4(a) when the divisor D is positive, and according to a table as shown in FIG. 4(b) when the divisor D is negative. However, hereupon, the divisor D and the partial remainder R.sub.j are as shown in the following expression, wherein r.sub.0, r.sub.1, r.sub.2 in FIG. 4(a) and FIG. 4(b) respectively show r.sub.j, 0, r.sub.j, 1, r.sub.j, 2 in the following expression. ##EQU5##
In this way, in the above-mentioned prior art, since there is no carry propagation in a division cycle, the division can be performed rapidly. Also, since the remainder is given in a binary difference, it is easy to convert it into a twos complementary representation.
However, since the tables for deciding the quotient digit are complicated, at the time of realizing quotient digit deciding means in integrated circuits and the like as actual circuits, a large number of transistors are required.
Besides, the divisor value must be standardized.
Furthermore, when the divisor is "-1", the divisor must be extended in a lower direction to make a least significant bit apparently "0".
Also, since such divider as aforementioned can not directly give and take data between a CPU and an ALU of a usual microcomputer, it is necessary to convert it into the twos complementary representation.